This application relies for priority upon Korean Patent Application No. 99-15923, filed on May 3, 1999, the contents of which are herein incorporated by reference in their entirety.
The present invention relates to a method for fabricating a semiconductor device, and more particularly to a method for fabricating a capacitor that can skip a CMP process with respect to an uneven interlayer insulating layer underlying a sacrificial oxide layer in which the capacitor is to be made.
An integrated circuit DRAM device typically includes many memory cells. In fact, a memory cell is provided for each bit stored by the DRAM device. Each individual memory cell typically consists of a storage capacitor and an access transistor. Either the source or the drain of the access transistor is connected to one terminal of the storage capacitor. The other side of the transistor""s channel and the transistor gate electrode are connected to external connection lines called a bit line and a word line, respectively. The other terminal of the capacitor is connected to a reference voltage.
The formation of a DRAM memory cell includes the formation of a transistor, of a capacitor, and of contacts to external circuits. The capacitor types that have been typically used in DRAM memory cells are planar capacitors, because they are relatively simple to manufacture.
However, in order to fabricate high density DRAM devices, the memory cells must be scaled down in size to the sub-micrometer range. This causes a reduction in capacitor area, resulting in the reduction of the cell capacitance. In this case, because the area of the charge storage capacitor is also decreased, the capacitance of the planar capacitor becomes relatively small. This decreases in storage capacitor leads to lowered signal-to-noise ratios and increased errors due to alpha particle interference. Accordingly, for very small memory cells, planar capacitors become unreliable.
In addition, as the capacitance decreases, the charge held by the storage capacitor must be refreshed more often, further degrading performance. A simple planar capacitor generally cannot provide sufficient capacitance for good performance, even with high performance dielectrics, such as Ta2O5.
Prior approaches to overcoming these problems have resulted in the development of the trench capacitor (see for example, U.S. Pat. No. 5,374,580) and the stacked capacitor (see for example, U.S. Pat. No. 5,021,357). Trench capacitors experience the well-known problem of xe2x80x9cgate diode leakage.xe2x80x9d Accordingly, stacked capacitors have been more widely fabricated recently.
For example, U.S. Pat. Nos. 5,763,304, 5,668,036, and 5,717,236, the disclosures of which are incorporated herein by reference, disclose a stacked capacitor that uses a chemical mechanical polishing (CMP) step with respect to an interlayer insulating layer on which the stacked capacitor is formed. In the conventional methods, a CMP process is carried out on the interlayer insulating layer because of its uneven surface topography. In a subsequent process, the CMP process is also carried out to electrically separate each storage node from one another.
As is well known, the CMP process suffers from the disadvantages of high expense, low throughput, process complexity, and high defect density. Accordingly, it would be very desirable to provide a method for fabricating a capacitor that can minimize the number of CMP processes required.
The present invention was made in view of the above problems, and is directed toward providing a method for fabricating a stacked capacitor that can minimize the use of CMP processes. In particular, the present invention omits a CMP process with respect to an interlayer insulating layer, but avoids causing problems mentioned above.
One of the features of the present invention is the formation of a CMP stopping layer on a sacrificial oxide layer to serve for CMP end point detection. Such a CMP stopping layer can make it possible to omit a CMP process with respect to the interlayer insulating layer.
Briefly, an interlayer insulating layer is formed over an integrated circuit substrate having undergone certain process steps, such as defining active and inactive regions, formation of transistors and formation of bit lines. Since transistors and bit lines are formed densely in the cell array region, and are formed sparsely in the peripheral region, there can arise a height difference (i.e., causing a step portion) in the surface of the interlayer insulating layer at the peripheral region. The interlayer insulating layer is preferably made of an oxide material selected from the group consisting of borophosphosilicate glass (BPSG) and undoped silicate glass (USG). More particularly, if a BPSG layer is formed, it is done so by the process of first depositing the BPSG, and then reflowing it at a predetermined temperature to provide a good surface topology.
Since conductive patterns are formed densely on the cell array region, the interlayer insulating layer has a substantially even surface over the cell array region. On the other hand, since conductive patterns are formed sparsely in the peripheral region, the interlayer insulating layer has an uneven surface topology over the peripheral region, i.e., it contains a step.
Contact plugs are then formed in the interlayer insulating layer. The contact plugs are electrically connected to the integrated circuit substrate. Unlike in the conventional method, a CMP process is not carried out on the interlayer insulating layer.
A sacrificial oxide layer is then deposited over the interlayer insulating layer, following the topography of the interlayer insulating layer. The sacrificial oxide layer is formed to a thickness at least the desired height of the storage node. This sacrificial oxide layer comprises an oxide material selected from the group consisting of BPSG, USG, phosphosilicate glass (PSG), spin on glass (SOG), hydrogen silsesquioxane (HSQ), and plasma enhanced tetraethylorthosilicate (PE-TEOS).
A CMP stopper layer is then formed over the sacrificial oxide layer, following the topography of the sacrificial oxide layer. The CMP stopper layer preferably comprises a material selected from the group consisting of silicon nitride, an alumina, a diamond-like carbon, aluminum nitride, and boron nitride. A second oxide layer may also be formed over the CMP stopping layer to provide a wide process margin for subsequent CMP processes.
Through photolithographic process, the second oxide layer, the CMP stopping layer, and the sacrificial oxide layer are etched to form trenches that expose the contact plugs. A conductive material, for the formation of the storage nodes, is then deposited in the trenches and over the second oxide layer. A CMP process is then carried out using the CMP stopping layer as an end point, to thereby form a storage node in the trench. The CMP stopping layer and any portions of the second oxide layer remaining over the CMP stopping layer at the lower portion of the step are then removed.
In method mentioned above, an etching stopper layer can also be formed prior to the formation of the sacrificial oxide layer. More specifically, after the formation of the contact plugs, an etching stopper layer, comprised of a nitride, may be deposited on interlayer insulating layer and the contact plugs. Alternately, the etching stopper layer can be formed formed on the interlayer insulating layer prior to the formation of the contact plugs. This etching stopper can allow a wide process margin during the formation of the trenches in the sacrificial oxide layer. Also, this etching stopper layer serves to increase capacitor area.
After removing the CMP stopping layer and any remaining second oxide layer, the sacrificial oxide layer outside the storage nodes is removed. In case that the etching stopper is formed on the interlayer insulating layer, it can be removed subsequent to the removal of the sacrificial oxide layer.
The method may also comprise forming a hemispherical grain (HSG) silicon layer on exposed portions of the conductive material, i.e., the storage nodes. This acts to increase the capacitance of a resulting capacitor.
In the alternative, a cylindrical stacked capacitor may be fabricated. In particular, after forming trenches for storage nodes in a frame insulating layer of a sacrificial oxide layer, a CMP stopping layer, and a second oxide layer, a conductive material is deposited in the trenches to only partially fill the trenches. Then a planarization insulating layer is deposited over the conductive material layer to completely fill the trenches. This planarization insulating layer in the trenches serves to protect the contamination of the interior trenches during subsequent CMP process. A CMP process is then carried out on the planarization insulating layer, the conductive material layer, and the second oxide layer, and stops at a top surface of the CMP stopping layer. Thus, a cylindrical storage nodes are formed in the trenches. The CMP stopping layer and any remaining second oxide layer are removed, and then the remaining planarization insulating layer in the interior trenches is removed to expose inner surfaces of the cylindrical capacitor storage nodes.
The method may also comprise forming a hemispherical grain (HSG) silicon layer on exposed portions of the conductive material, i.e., the cylindrical storage nodes. This acts to increase the capacitance of a resulting capacitor. The forming of a hemispherical grain (HSG) silicon layer may be performed before planarizing portions of the conductive material and the upper insulating layer, or it may be performed after planarizing portions of the conductive material and the upper insulating layer.
In accordance with one aspect of the invention, a method is provided for fabricating a capacitor in an integrated circuit device. This method comprises forming a lower insulating layer having an uneven surface topology over an integrated circuit substrate, forming a contact plug electrically connected to the integrated circuit substrate in the lower insulating layer, forming an upper insulating layer over the lower insulating layer and the contact plug, the upper insulating layer including a planarization stopper, etching the upper insulating layer to form a trench that exposes the contact plug and the lower insulating layer around the contact plug, depositing a conductive material in the trench and over the upper insulating layer, planarizing portions of the conductive material and the upper insulating layer until a top surface of the planarization stopper is exposed to electrically isolate remaining conductive materials inside the trenches from another, and removing remainders of the upper insulating layer until the lower insulating layer is exposed.
The method may further comprise forming an etching stopper over the lower insulating layer, prior to forming the upper insulating layer, and etching the etching stopper after removing the upper insulating layer.
The process of forming the upper insulating layer may itself further comprise forming a first oxide layer over the lower insulating layer, forming a planarization stopper layer over the first oxide layer, and forming a second oxide layer over the planarization stopper layer.
The planarizing of portions of the conductive material and the upper insulating layer preferably includes planarizing the conductive material and portions of the second oxide layer until the top surface of the planarization stopper layer is exposed.
The removing of remainders of the upper insulating layer until a top surface of the lower insulating layer is exposed, may itself comprise removing a remainder of the second oxide layer on the planarization stopper layer, removing the planarization stopper layer, and removing the first oxide layer.
The depositing of the conductive material may further comprise partially filling the trench with the conductive material and completely filling the remainder of the trench with an insulating material. The insulating material is preferably removed from the trench after the removing of remainders of the upper insulating layer.
In accordance with an alternative aspect of the invention, a method is provided for fabricating a capacitor in an integrated circuit device. This method comprises forming a first insulating layer over an integrated circuit substrate, the integrated circuit substrate having a step portion, etching the first insulating layer to form a contact opening to expose the integrated circuit substrate, filling the contact opening with a first conductive material to form a contact plug, forming a second insulating layer over the first insulating layer and the contact plug, forming a planarization stopper over the second insulating layer, forming a third insulating layer over the planarization stopper, etching the third insulating layer, the planarization stopper, and the second insulating layer to form a trench that exposes the contact plug, forming a conductive layer in the trench and over the third insulating layer, planarizing the conductive layer and the third insulating layer and stopping at a top surface of the planarization stopper to thereby form storage nodes inside the respective trenches, removing remainders of the third insulating layer on the planarization stopper at a lower part of the step portion, and removing the planarization stopper and the second insulating layer to expose an outer sidewall of the storage node of the capacitor.
The method may also comprise forming a hemispherical grain (HSG) silicon layer on the storage node.
The method may also comprise forming an etching stopper prior to forming the second insulating layer. This etching stopper is preferably made of a material having an etching selectivity with respect to the second insulating layer. In particular, the etching stopper preferably comprises a material selected from the group consisting of silicon nitride, alumina, diamond-like carbon, aluminum nitride and boron nitride.
The planarization stopper preferably comprises a material having an etching selectivity with respect to the second and third insulating layers. In particular, the planarization stopper preferably comprises a material selected from the group consisting of silicon nitride, alumina, diamond-like carbon, aluminum nitride and boron nitride.
The first insulating layer preferably comprises an oxide selected from the group consisting of borophosphosilicate glass (BPSG) and phosphosilicate glass (PSG). The second and third insulating layers are preferably made independently, and each preferably comprises a material selected from the group consisting of borophosphosilicate glass (BPSG), phosphosilicate glass (PSG), spin on glass (SOG), hydrogen silsesquioxane (HSQ), and plasma enhanced tetraethylorthosilicate (PE-TEOS).
In accordance with another aspect of the invention, a method for fabricating a capacitor in an integrated circuit device is provided that comprises providing an integrated circuit substrate having a cell region and peripheral region, forming a plurality of first transistors in the cell region, forming a plurality of second transistors in the peripheral region, forming a plurality of landing pads between the first transistors, forming a first insulating layer over the integrated circuit substrate to insulate the first and second transistors and the landing pads, densely forming a plurality of bit lines over the first insulating layer in the cell region, sparsely forming a plurality of local interconnections over the first insulating layer in the peripheral region, forming a second insulating layer over the first insulating layer, the plurality of bit lines and the plurality of local interconnections, the second insulating layer being conformal and following the contours of the underlying local interconnections and the first insulating layer, thereby causing a step portion to form in the peripheral region, etching the second insulating layer and the first insulating layer to form a plurality of contact openings exposing corresponding landing pads, filling the contact openings with a conductive material to form a plurality of contact plugs, forming an etching stopper over the second insulating layer and the contact plugs, forming a third insulating layer over the etching stopper, the third insulating layer defining a height of a storage node, forming a planarization stopper over the third insulating layer, forming a fourth insulating layer over the planarization stopper, etching the fourth insulating layer, the planarization stopper, the third insulating layer, and the etching stopper to form a plurality of trenches that expose the contact plugs, forming a conductive layer in the trenches and over the fourth insulating layer, planarizing the conductive layer and the fourth insulating layer and stopping at a top surface of the planarization stopper to thereby form storage nodes inside the respective trenches, removing remainders of the fourth insulating layer over the planarization stopper at a lower part of the step portion in the peripheral region, and removing the planarization stopper and the third insulating layer to expose outer sidewalls of the storage nodes.
The etching stopper and the planarization stopper are preferably made independently, and each preferably comprises a material selected from the group consisting of silicon nitride, an alumina, a diamond-like carbon, aluminum nitride and boron nitride. The third and fourth insulating layers are preferably made independently, and each preferably comprises a material selected from the group consisting of borophosphosilicate glass (BPSG), phosphosilicate glass (PSG), spin on glass (SOG), hydrogen silsesquioxane (HSQ), and plasma enhanced tetraethylorthosilicate (PE-TEOS).
In addition, the method may further comprise forming a hemispherical grain (HSG) silicon layer on the storage nodes.